1. Field
Embodiments of the present disclosure relate to a semiconductor memory technique, and more particularly, to a method of initializing a 3D non-volatile memory device.
2. Description of the Related Art
Due to increasing demands for portable application devices, such as digital cameras, smart phones, and tablet PCs, and replacement of conventional hard disk drives with solid-state drives (SSDs), markets for non-volatile memory devices are rapidly growing. Among these non-volatile memory devices, NAND flash memory devices are popular due to low manufacturing cost for high degree of integration.
Recently, downscaling the NAND flash memory device with a conventional two-dimensional (2D) memory cell array architecture has become more difficult as 20 nm or smaller photolithography techniques have reached their limits. In addition, design issues, which are related to reduction of a sensing margin in accordance with reduction of a number of electrons stored in a data storage film (e.g., a floating gate), and related to disturbances between memory cells, have become barriers against the downscaling of the conventional 2D memory cell array architecture.
To address the issues for downscaling a NAND flash memory device, various 3D NAND flash array structures have been suggested. For example, the Korean Patent Laid-Open Gazette No. 10-2011-011166 discloses a “layer selection by erase operation (LASER)” structure having a channel-stacked array structure, the entire disclosure thereof is incorporated herein in its entirety by reference. Unlike conventional 2D flat-panel type memory arrays, the 3D LASER structure requires a memory layer selection with respect to stacked memory layers for a read operation, a write operation, or an erase operation, where the memory layer selection is performed based on combinations of string selection transistors with one another. As another example for the 3D NAND flash memory device having memory layer selecting mechanism based on a “layer selection by multi-level operation (LSM)” using multi-level string selection transistors has been suggested.
To select a memory layer in the various 3D NAND flash memory devices, such as based on the LASER structure and the LSM structure, it is desirable to program or initialize string selection transistors to cause them to have certain threshold values. It is required to obtain a sharp distribution of threshold values of programmed string selection transistors, and further desirable to program the string selection transistors without an interlayer disturbance between memory arrays. In addition, while a programming bias is applied to a selected wordline coupled with a selected memory cell to program the selected memory cell, for a reliable program operation on the selected memory cell, it is preferable not to cause any disturbance to other memory cells sharing the selected wordline.
In order to program or initialize the string selection transistors, it is generally required to incorporate and utilize a dummy string selection transistor into a memory string. As the dummy string selection transistor may be a redundancy, it may become an obstacle to be overcome for downscaling 3D non-volatile memory devices.